Room: MCLD 3038, Bldg: MacLeod Building, 2356 Main Mall, Vancouver, British Columbia, Canada, V6T 1Z4

Technical seminar by Professor David Keezer, IEEE Life Fellow, Chair Professor at EIT, NingboToday’s integrated circuits may contain billions of transistors and operate at multiple gigahertz clock rates. The communication port input and output aggregate bandwidths can easily exceed a terahertz (e.g. 800G and 1.6T PCIe and fiber-optic ports). Furthermore, some ICs support multiple high-speed communication ports as well as high-performance analog/RF signals. All these critical features need precise testing to ensure product quality. While existing automated test equipment (ATE) can handle the bulk of “mainstream” IC test requirements, they are not well-suited for these most advanced applications and are not easily adapted to new test challenges of future devices that may use entirely new signaling protocols. There is therefore a “gap” between the ability of ATE and the test needs of the most advanced devices. To address this problem, we are assembling an FPGA-based test-development platform that can quickly adapt to future test requirements. This presentation will describe the strategy and system architecture and show some early demonstrations for testing mixed analog/digital ICs as well as communication channels operating up to 224 Gbps per <a href="http://lane.Speaker(s):" target="_blank" title="lane.Speaker(s):">lane.Speaker(s): David Keezer, Room: MCLD 3038, Bldg: MacLeod Building, 2356 Main Mall, Vancouver, British Columbia, Canada, V6T 1Z4