Co-Packaged Optics – 3D Heterogeneous Integration of Photonic IC and Electronic IC

Technical seminar by IEEE Electronics Packaging Society Distinguished Lecturer Dr. John H. Lau with the following abstract:

Silicon photonics are the semiconductor integration of EIC and PIC on a silicon substrate (wafer) with complementary metal-oxide semiconductor (CMOS) technology. On the other hand, co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) and the electrical engine (EE) which consists of the electronic ICs (EIC) as well as the switch ASIC (application specific IC). The advantages of CPO are: (a) to reduce the length of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC, (b) to reduce the energy required to drive the signal, and (c) to cut the latency which leads to better electrical performance. In the next few years, we will see more implementations of a higher level of heterogeneous integration of PIC and EIC, whether it is for performance, form factor, power consumption or cost. The content of this lecture is shown <a href="http://below.

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– Silicon Photonics
– Data Centers
– Optical Transceivers
– Optical Engine (OE) and Electrical Engine (EE)
– OBO (on-board optics)
– NPO (near-board optics)
– CPO (co-packaged optics)
– 3D Integration of the PIC and EIC
– 3D Heterogeneous Integration of PIC and EIC
– 3D Heterogeneous Integration of ASIC Switch, PIC and EIC
– 3D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges
– 3D Heterogeneous Integration of ASIC Switch, EIC and PIC embedded in Glass-core Substrate
– Summary and Recommendations

Speaker(s): John Lau,

Room: MCLD 3038, Bldg: MacLeod Building , 2356 Main Mall, Vancouver, British Columbia, Canada, V6T 1Z4