The Road to Gate-All-Around CMOS

Technical talk with the following abstract:

Despite the much debated end of Moore’s Law, CMOS scaling still maintains economic relevance with 3nm finFET SoCs already in the marketplace for three years and 2nm gate-all-around SoCs anticipated late this year. Area scaling extensively driven by design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges. This will set the context for motivating the transition to the gate-all-around device architecture, namely nanoribbons or nanosheets, and unveiling the magic of how these devices are <a href="http://fabricated.

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Speaker(s): Alvin Loke,

Room: CEME 1202, Bldg: Civil and Mechanical Engineering Building, 6250 Applied Science Lane, Vancouver, British Columbia, Canada, V6T 1Z4