Room: 460, Bldg: ENG, 245 Church Street, Toronto, Ontario, Canada, M5B 2K3

Join us to explore the world of Pre-Silicon ASIC Validation (also known as Functional or Design Verification), which plays a pivotal role in delivering functional silicon at IP and SoC levels—powering the experiences, products, and services we rely on <a href="http://today.You" target="_blank" title="today.You">today.You will gain insight into the goals and challenges of validation, potential career paths, and the opportunities for innovation in this field. As yesterday’s SoCs—complete with digital, analog, CPU subsystems, and software—evolve into today’s IP blocks, you’ll learn how validation methodologies and tools have scaled to meet these massive technical <a href="http://hurdles.Beyond" target="_blank" title="hurdles.Beyond">hurdles.Beyond high-level strategy, you’ll walk away with a functional understanding of a UVM (Universal Verification Methodology) environment—the industry mainstay for simulation—and the tool automation used to navigate vast validation spaces. A brief demonstration will showcase how constrained-random techniques generate stimulus to exercise a design, exposing bugs that engineers often never imagined <a href="http://existed.Audience" target="_blank" title="existed.Audience">existed.Audience questions and interaction during and after the talk are enthusiastically encouraged!Room: 460, Bldg: ENG, 245 Church Street, Toronto, Ontario, Canada, M5B 2K3