Room: 3142, Bldg: EIT, ECE Department, 200 University Ave. W., Waterloo, Ontario, Canada, N2L 3G4
Events at this venue
-
-
SSCS Distinguished Lecture: “Rethinking Chip Design in the Age of AI”
Room: 3142, Bldg: EIT, ECE Department, 200 University Ave. W., Waterloo, Ontario, Canada, N2L 3G4Abstract: AI is changing not only the applications we build, but also the way we design the chips that power them. This talk explores how we can rethink chip design in the age of AI from two complementary directions: using AI to automate and improve chip design, and building specialized chips that make AI dramatically more <a href="http://efficient.On" target="_blank" title="efficient.On">efficient.On the design side, we present Agentic-RL gLayout, a reinforcement-learning framework for analog layout generation that replaces manual heuristics with goal-driven planning and self-correction. Built on open-source tools such as OpenROAD, gLayout, and OpenFASOC, it enables cleaner, more compact, and rule-compliant layouts with far less manual effort. On the architecture side, we present a hardware-software co-design stack for efficient edge AI, reducing latency and energy in LLM inference. By co-optimizing models, precision, and accelerator design, this approach supports fast, privacy-preserving inference under tight power <a href="http://constraints.Taken" target="_blank" title="constraints.Taken">constraints.Taken together, these efforts illustrate a broader shift toward open, AI-enabled chip design flows and domain-specific AI hardware. The result is a faster, more automated, and more accessible path to silicon in the age of <a href="http://AI.Speaker(s):" target="_blank" title="AI.Speaker(s):">AI.Speaker(s): Mehdi, Room: 3142, Bldg: EIT, ECE Department, 200 University Ave. W., Waterloo, Ontario, Canada, N2L 3G4
-
Research and Open-Source EDA Tools
Room: 3142, Bldg: EIT, ECE Department, 200 University Ave. W., Waterloo, Ontario, Canada, N2L 3G4Abstract: This presentation describes the IC design flow when performing research with open-source, non-academic EDA tools. The tools maintained and develop by Tim are used as examples (e.g., magic, netgen, capiche, open_pdks, and others), but he will discuss other commercial and organizational open-source tools, such as OpenROAD, LibreLane, and others. Tim’s talk is outlined below:(1) History of open-source EDA tools(2) Magic's cutting edge (at the time) DRC and parasitic extraction(3) The Dark Ages of Open-Source EDA(4) The first open PDK development: Efabless, Google, and SkyWater(5) Circuit design and synthesis examples: MultiGiG to Raven to today(6) Magic's extraction revisited: FasterCap and Capiche(7) Hierarchical R-C extraction with analytical capacitor modelsSpeaker(s): Tim, Room: 3142, Bldg: EIT, ECE Department, 200 University Ave. W., Waterloo, Ontario, Canada, N2L 3G4